The most common practice of the prior art in data signal triggering/sampling is to use a clock returned from a chip pin to trigger/sample the data signal, but this method has three shortcomings as follows:
1) When testing and verifying by using FPGAs (Field-Programmable Gate Array), the stability of timing characteristics can only be guaranteed by employing a trigger using the global clock network, and therefore, if a register is directly triggered by the clock returned from the chip pin, the timing characteristics of the register will not be guaranteed and setup/hold timing violations may occur, which will be reflected as instability during the test.
2) When implementing by using ASICs (Application Specific Integrated Circuit), both signal delay from the register's Q-end to the chip pins and signal delay from the chip pins to the register's D-end must be accurately controlled so as to obtain a satisfying setup/hold time.
3) Sampling locations are not adjustable, leading to the lack of flexibility and the proneness to be limited by a delay in the circuit of the test board.
As shown in FIGS. 1 and 2, Tpd is the sum of the chip internal delay and the test board delay; Tset is the setup time needed for the data receiving end to sample data; and Thold is the hold time needed for the data receiving end to sample data. In FIG. 1, a forward delay of data signal against clock takes up the setup time of the data receiving end, and in FIG. 2, a backward delay of data signal against clock takes up the hold time of the data receiving end. Thus, it is clear that fixed trigger/sampling points will be affected by signal delay.
Currently, SD card (Secure Digital Memory Card) and SDIO card (Secure Digital Input and Output Card) have been widely used in handheld devices, and there are many designs for the host controller of an SD/SDIO card. However, as trigger/sampling points cannot be flexibly arranged at the end of SD/SDIO cards, the setup/hold time issues caused by signal delay are mostly solved through accurately controlling the chip internal delay, thus resulting in a number of limitations. Therefore, to solve this problem, it is necessary to propose technical means that will enable the configurability of trigger/sampling points in SD/SDIO host controllers.